In recent years, the development of flat-screen display apparatuses such as liquid crystal display apparatuses and organic EL display apparatuses has been advanced at a rapid pace. Such flat-screen display apparatuses often have an active matrix substrate where a switching element for driving a pixel is placed for each of a plurality of pixels for the purpose of enhancing the display quality.
The display apparatus has the above active matrix substrate and a counter substrate opposed to the active matrix substrate and bonded thereto via a frame-shaped sealing member. The display apparatus has a display region formed inside the sealing member, and also has a non-display region outside the periphery of the display region.
A thin film transistor (TFT), for example, as the switching element for each of a plurality of pixels is formed in a region of the active matrix substrate that is to serve as the display region. A semiconductor layer of the TFT was used to be formed of amorphous silicon (a-Si), etc. Recently, however, attempts have been made to form the semiconductor layer of an oxide semiconductor such as In—Ga—Zn—O (IGZO) in place of a-Si.
Such an oxide semiconductor, constructed by highly ionic bonding, is small in the difference in the mobility of electrons between its crystalline state and its amorphous state. Therefore, a comparatively high electron mobility is obtained even in the amorphous state.
Patent Document 1 discloses a bottom-gate type TFT. As shown in FIG. 25 that is an enlarged plan view, a TFT 100 includes: a gate electrode 101 formed on a substrate; a semiconductor layer 102 formed to cover the gate electrode 101 via a gate insulating film; a source electrode 103 overlapping the semiconductor layer 102 at one end of the semiconductor layer 102; and a drain electrode 104 overlapping the semiconductor layer 102 at the other end thereof. The gate electrode 101, the semiconductor layer 102, the source electrode 103, and the drain electrode 104 are individually formed into their predetermined shapes by photolithography and etching.
If the source electrode 103 and the drain electrode 104 are displaced at the time of photolithography protruding from the semiconductor layer 102, the overlap areas thereof with the semiconductor layer 102 will decrease, decreasing the channel width of the TFT 100.
To avoid the above problem, in order to keep the channel width constant even if the source electrode 103 and the drain electrode 104 are somewhat displaced, the width A of the semiconductor layer 102 in the channel width direction (vertical direction in FIG. 25) is made larger than the width B of the source electrode 103 and the drain electrode 104 in the channel width direction.
That is, the semiconductor layer 102 is formed wider than the source electrode 103 and the drain electrode 104 by the value of (width A−width B) as a superposition margin with the source electrode 103 and the drain electrode 104.